Research on High-Speed Data Transmission Model of Large-Format High-Frame-Rate Readout Integrated Circuit

In this paper, a high-speed data transmission model is presented for the digital signal output of a large-format high-frame-rate readout integrated circuit. We utilize the lumped parameter model to investigate the relationship between 3 dB bandwidth, response time, and device parameters. It is indicated that the size of the driver and the load of the transmission bus are the key parameters that determine the high-speed time-domain response characteristics. Furthermore, by using the distributed parameter model and Elmore delay model, the analytic expression for response time is deduced with more accurate values, and the optimal design of the output stage toward maximum bandwidth is obtained. Under the typical constraint condition of layout and power dissipation in a 64×64 array, simulation results show that the output 3 dB bandwidth of the transmission gate and composite logic gate can reach 293 MHz and 395 MHz, respectively.